Data transmission across communications networks has continued to gain widespread use throughout the world. Typically, data is transmitted over communications networks by first partitioning a message or data into data packets according to network protocol. The data packets may then be transmitted across a communications network, each packet likely taking their own route to get to the desired location. After transmission, processing circuitry on the receiving end of the transmission reconstructs the data packets into the message or data originally transmitted.
To ensure the accuracy of the data transmitted across a network, and to detect transmission errors as soon as they occur, various techniques have been implemented over the years. Perhaps the most popular technique is to append Cyclic Redundancy Check (CRC) values to the data packets before they are transmitted across the network. As each data packet is received, a CRC calculation is performed on each data packet to produce a CRC value. This CRC value is compared to the CRC value appended to the data packet to determined if they are the same. If data has been lost or corrupted during transmission, the comparison of CRC values usually detects the error.
CRC processing logic is often implemented using a parallel architecture due to the high data transmission rates now being supported, as well as limitations on practical and cost effective processor cycle times. In such an architecture, CRC values are calculated over multiple data bits each clock cycle. Typically, conventional implementations are based on an internal databus having a given width (n×8 bits, where “n” is the number of bytes in the bus-width). Although data packets typically vary in length, data packet transmission standards usually set packet length variation on a given boundary, for example, on an 8-bit boundary. As a result, each incoming data packet is typically analyzed by viewing each data packet in segments, some having the full given bus-width of data, and the last segment possibly having only a byte-wide sub-multiple of the overall bus-width for the network.
In the commonly found parallel architecture CRC calculation systems, updated CRC values are calculated each clock cycle as a function of a CRC value calculated the previous clock cycle and data coming from the current segment. To calculate an intermediate CRC value for those segments of a data packet where all the bytes therein are present, a predetermined amount of logic is required based, in part, on the size of the boundary set by the network standard. Although the logic employed to calculate this intermediate CRC value is complex, based primarily on the size of the equations needed to calculate all of the bytes in the predetermined segment width, the logic does not vary since all of the available bytes of the segments processed with this logic are present.
Unfortunately, when the final CRC calculation is performed on the last segment, the logic required may become much more complex. Since any number of the maximum number of bytes in a final segment may or may not be present, logic capable of calculating each of the different possibilities is typically required. More specifically, the logic employed to calculate the remaining CRC value for the final segment must account for the relationship between the previously calculated CRC value and one, two, three, . . . n−1 bytes of an incomplete final segment in an n-byte wide bus. Those who are skilled in the art understand that conventional CRC calculation systems accounting for so many variable relationships would typically require large and complex logic circuitry within the chip or other structures within the communications device. This is the case because the equations used in such calculations become similarly large and complex as the number of possible relationships increase. In many cases, separate logic is needed for each possibility. For example, where a data packet is partitioned into n-byte segments for an n-byte wide bus, an incomplete final segment would require n−1 sets of different logic circuits just to calculate a CRC value for the final segment of a data packet.
Semiconductor manufacturers understand that as the amount of logic required increases, so also does the costs of manufacturing the device. In addition, greater surface area is taken as the complexity of the logic circuitry increases. Therefore, the downsizing of communications devices can become problematic, as does the use of limited logic devices, such as Field Programmable Gate Arrays (FPGAs) and Field Programmable System Chips (FPSCs) throughout communications networks.
Accordingly, what is needed in the art is an enhanced CRC calculation system for calculating a CRC value for data packets having partial data segments that does not suffer from the deficiencies found in conventional CRC calculation systems.